The architecture of the 8086 Microprocessor

The architecture of the 8086 Microprocessor

The architecture of the 8086 Microprocessor

 

 

 

 BUS INTERFACE UNIT(BIU):

• It is the interface of 8086 from external devices
•  It operates with respect to bus cycles.
• it is responsible for external bus operation.
• It performs the following function
• it generates the 20-bit physical address for memory access.
• fetches opcode from memory.
• transfer the data to and from memory and I/o

The main component of BIU is the segment resistor.

•  cs register ( code segment )

It holds the base address for program memory ( code segment ).these base address when multiply by 10 H  (16-bit) gives a 20-bit starting address of the code segment.
Eg. : CS = 4321H
CS =4321H × 10 H=43210H

• Ds register ( data segment )

It holds the base address for data segment .these base address when multiply by 10 H  (16 bit ) that gives a 20 bit starting address of  the data  segment .
Eg. : DS = 4321H
DS =4321H × 10 H=43210H

•  SS register ( stack segment )

It holds the base address for the stack segment .these base address when multiplied by 10 H  (16-bit) gives a 20-bit starting address of the stack segment.
Eg. : SS = 4321H
SS =4321H × 10 H=43210H

• ES register ( extra segment ):

It hold the base address for the extra segment .these base address when multiplied by 10 H  (16-bit) gives a 20 bit starting address of  the extra  segment .
Eg. : ES = 4321H
ES =4321H × 10 H=43210H

• Instruction pointer 
•  It is a 16-bit resistor. It holds the offset of the next instruction in the code segment.
• IP is incremented after every instruction byte is fetched.
• address of the next instruction is calculated as
• Next address = cs × 10 H + IP
• IP gets a new value whenever a branch occurs.

•  Address generation circuit :

Physical address = (segment address× 10 H )+ offset address

• 6-BIT INSTRUCTIONS QUEUE:
• It is 6-bit 1st input and 1st output.
• It fetches 6 instruction bites until the queue is full.
•  to fetch the instruction bit at least two bits of the queue must be empty.
•  Fetching the next instruction while executing the current instruction is called "Pipelining" 
•  Pipelining increases the efficiency of the microprocessor.

2) EXECUTION UNIT ( EU):

• It fetches the instruction from the instruction queue and decodes the instruction and executes it.
•  It performs athematic logical decision-making and data operations.
•  It sends a request signal to the BIU to excess to the external module.
• It does not operate with respect to bus cycle but operates with 8086

The main components of the execution unit:-

(1) General purpose register

8086 has 4 16-bit general purpose accumulator base register counter data these are available for the program of these registers can be divided into beat register AH AL BH BL CH CL DH DL

• Ax register: 16-bit used as an accumulator for multiplication and division operations also it holds the result of multiplication lower 16-bit and division in consent it always core data during input and output data transfer in and out instruction
• BX RESISTOR: hold the memory address in indirect addressing mode along with SI.
• CX resistor: The resistor holds the count for the following instruction, Loop intrusion indicates no
• DX resistor: It is used to hold the address of the I/o  port.

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